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Proceedings of

International Conference on Future Trends In Electronics and Electrical Engineering FTEE 2013

"A LOW-POWER SAMPLE-AND-HOLD AMPLIFIER USING 0.05-µM CMOS TECHNOLOGY"

HIMANSHU PUNDIR RITURAJ SINGH RATHORE VINOD KUMAR
DOI
10.15224/978-981-07-7021-1-40
Pages
38 - 41
Authors
3
ISBN
978-981-07-7021-1

Abstract: “This paper presents a sample-and-hold circuit based on a cascode-miller compensation technique, utilizing a class-AB operational amplifier as an output stage. Also using the techniques of pre-charging and output capacitor coupling can mitigate the requirements for the op-amp, resulting in low power dissipation. Power consumption is about 300µW from a single 1-V power supply. The performance of this SHA is not degraded even if input frequency approaching up to Nyquist frequency.”

Keywords: — Sampling, Sample and Hold (SHA), ADC (Analog to Digital Converter), Power Consumption.

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