IRED conference proceeding article -Delay Analysis in Carbon Nanotube Bundle Interconnect For VLSI Design

Proceedings of

Second International Conference on Advances In Electronics, Electrical And Computer Engineering EEC 2013

"DELAY ANALYSIS IN CARBON NANOTUBE BUNDLE INTERCONNECT FOR VLSI DESIGN"

DEVENDERPAL SINGH MAYANK KUMAR RAI

DOI

10.15224/978-981-07-6935-2-66

Pages

321 - 326

Authors

ISBN

978-981-07-6935-2

Abstract: “This paper proposes to study the performance of carbon nanotube bundle in terms of delay as a VLSI interconnect at 32nm technology node. Output waveform and 90% propagation delay are analytically determined and compared with SPICE simulation result. Alpha power law model is used for representing the transistors of CMOS driver. SPICE simulation result reveals that delay increases with increase in length of interconnect.”

Keywords: Carbon Nanotubes, Interconnect, Propagation Delay, L-segment RLC

Second International Conference on Advances In Electronics, Electrical And Computer Engineering EEC 2013

"DELAY ANALYSIS IN CARBON NANOTUBE BUNDLE INTERCONNECT FOR VLSI DESIGN"

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