Abstract: “This paper presents a design of a 8 transistor one-bit full adder cell with Double Gate MOSFET. This design has been compared with existing 8 transistor one-bit full adder cell using Single Gate MOSFET at 45nm technology in sub threshold region. In this paper, the designed circuits are observed keeping the power consumption and Power Delay Product as parameters. Simulations are performed on SPICE tool and they have verified the correct operation of the full adder cell using Double Gate MOSFET for a variety of inputs at different supply voltages, temperatures and frequencies. Results indicated that the full adder with Double Gate MOSFET is capable of significant improvement in power consumption and Power Delay Product.”

Keywords: DG MOSFET, full adder, low power, PDP, subthreshold.