Abstract: “This paper presents an equivalent RC delay approach to study the subthreshold operation for inverter and OR logic circuits. The inverter is designed for subthreshold current model, which is exponential in nature instead of using square law model. Based on the inverter the other Domino circuits are designed and various bulk biasing techniques are used. Taking the effect of Miller capacitance, equivalent capacitance is calculated and results of RC delay are compared with SPICE simulation in 32nm technology.”

Keywords: Low power, Subthreshold, Dynamic logic circuit