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Proceedings of
International Conference on Advanced Computing, Communication and Networks CCN 2011
"HIGH THROUGHPUT-LESS AREA EFFICIENT FPGA IMPLEMENTATION OF BLOCK CIPHER AES ALGORITHM"
D.MAHESH KUMAR
M.SIRIN KUMARI
Y.RAMA DEVI
DOI
10.15224/978-981-07-1847-3-1027
Pages
484 - 489
Authors
3
ISBN
978-981-07-1847-3-1027
Abstract: “This paper addresses design, hardware implementation and performance testing of AES algorithm. An optimized code for the Rijndael algorithm with 128-bit keys has been developed. The area and throughput are carefully trading off to make it suitable for wireless military communication and mobile telephony where emphasis is on the speed as well as on area of implementation. Keywords: Cryptography, Rijndael, Encryption,Advanced Encryption Standard (AES), pipelining,security, very-large-scale integra”
Keywords: Cryptography, Rijndael, Encryption,Advanced Encryption Standard (AES), pipelining,security, very-large-scale integration (VLSI), VHDL.