Abstract: “Memory devices are critical components of electronic systems. And with increasing complexity brought about by greater end market demands, next-generation systems require newer memory architectures. For networking infrastructure applications, the memory devices required are typically high-density, high performance, high bandwidth memory devices with a high degree of reliability. For very high speed data communication system Designer need faster processors, faster memory and high speed interfacing peripheral components. While the processors in these systems have improved in performance, static memories have been unable to keep up the pace. Newer SRAM architectures have evolved to support the higher throughput requirements of current systems and processors. This application note introduces QDR, which is an SRAM architecture designed to improve the SRAM interface bandwidth by more than four times that of the current solutions. This paper summarizes that for high performance as well as high”

Keywords: QDR II SRAM, QDR II Controller, User Interface, Physical interface, UART, Burst length, Bus Width.