Abstract: “Recently, autonomous vehicles and robots demand high-speed image recognition capability that is superior to that of the human eye, in addition to capability of recognizing various natural images just like humans can. However, to realize both, the bus bandwidth of current memories is insufficient. Such an embedded system necessitates the use of numerous highresolution template images on a memory. Although the amount of memory is always sufficient, the transfer speed of template images is insufficient. To increase the number of recognition images, the number of template images must be increased. In addition to realizing rapid recognition, numerous template images must be transferred to a processor. Then a matching operation must be executed within an extremely short period. However, achieving such high-speed real-time image recognition operation is difficult because of the bottleneck of the bus bandwidth between the memory and processor. A dynamically reconfigurable vision architecture i”

Keywords: Field programmable gate arrays, Optically reconfigurable gate arrays