EXPLOITING SELF-ADAPTIVE, 2-WAY HYBRID FILE ALLOCATION ALGORITHM
Published In: 3RD INTERNATIONAL CONFERENCE ON ADVANCES IN COMPUTING, ELECTRONICS AND COMMUNICATION
Author(s): JAECHUN NO , SUNG-SOON PARK
Abstract: We present hybridFS file system that provides a hybrid structure, which makes use of performance potentials of NAND flash-based SSD (Solid-State Device). As the technology of flash memory has rapidly improved, SSD is being used in various IT products as a nonvolatile storage media. Applications looking for better I/O performance attempt to achieve desirable bandwidth, by employing SSD to storage subsystems. However, building a large-scale SSD storage subsystem deploys several issues that need to be addressed. Those issues include peculiar physical characteristics related to flash memory and high SSD cost per capacity compared to HDD devices. This paper presents a new form of self-adaptive, hybrid file system, called hybridFS, which properly attempts to address aforementioned issues. The main goal of hybridFS is to combine attractive features of both HDD and SSD devices, to construct a large-scale, virtualized address space in a costeffective way. The performance evaluation shows that h
- Publication Date: 11-Oct-2015
- DOI: 10.15224/978-1-63248-064-4-28
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PREDICTABLE CPU ARCHITECTURE DESIGNED FOR SMALL REAL-TIME APPLICATIONS – IMPLEMENTATION RESULTS
Published In: 3RD INTERNATIONAL CONFERENCE ON ADVANCES IN COMPUTING, ELECTRONICS AND COMMUNICATION
Author(s): IONEL ZAGAN , VASILE GHEORGHITA GAITAN
Abstract: The purpose of this paper is to describe and present the implementation results of nMPRA-MT processor concept designed for small real-time applications. Our target is to validate a fine-grained multithreading CPU architecture that uses replication and remapping techniques for the program counter, general purpose registers and pipeline registers. The new predictable CPU implementation is based on a hardware scheduler engine, being able to schedule dynamically a set of tasks on the five-stage pipeline assembly line. Using a FPGA device from Xilinx, we validate the innovative nMPRA-MT processor, interleaving different types of threads into the pipeline assembly line, providing predictability and hardware-based isolation for hard real-time threads. Mechanisms for synchronization and inter-task communication are also taken into consideration
- Publication Date: 11-Oct-2015
- DOI: 10.15224/978-1-63248-064-4-29
- Views: 0
- Downloads: 0