IMPLEMENTATION OF GF (216) MULTIPLIER USING COMBINATIONAL GATES
Published In: 2ND INTERNATIONAL CONFERENCE ON ADVANCES IN COMPUTING, CONTROL AND NETWORKING
Author(s): AADITI BHOITE , MOHINI SAWANE , SHWETA GARTHE
Abstract: This paper proposes the design and implementation of GF (216) multiplier using composite field arithmetic. We have introduced an irreducible polynomial X2+X+ξ. This irreducible polynomial is required for transforming Galois field of GF (216) to composite field of GF (((22)2)2)2. Our estimation of the value of ξ and subsequently the composite field arithmetic hence forth derived achieved high speed GF (216) multiplier. The design being purely combinational is a clock free design. We achieved critical path delay of 11.5ns between inputs to output data path. We have used combination of ᴪ and λ as {10}2 and {1100}2 respectively. Due to this value of ᴪ, λ, ξ we achieved fastest implementation, at the cost of few extra gates. The design methodology includes implementation and verification on FPGA using Xilinx ISE and finally the physical layout was designed on ASIC using 90nm CMOS standard cell libraries. Our implementation result shows that without pipelining the hardware core can achieve t
- Publication Date: 29-Aug-2015
- DOI: 10.15224/978-1-63248-073-6-04
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PRELIMINARIES ON A HARDWARE-BASED APPROACH TO SUPPORT MIXED-CRITICAL WORKLOAD EXECUTION IN MULTICORE PROCESSORS
Published In: 2ND INTERNATIONAL CONFERENCE ON ADVANCES IN COMPUTING, CONTROL AND NETWORKING
Author(s): BRUNO GREEN , FABIAN VARGAS
Abstract: The use of multicore processors in general-purpose real-time embedded systems has experienced a huge increase in the recent years. Unfortunately, critical applications are not benefiting from this type of processors as one could expect. The major obstacle is that we may not predict and provide any guarantee on real-time properties of software running on such platforms. The shared memory bus is among the most critical resources, which severely degrades the timing predictability of multicore software due to the access contention between cores. To counteract this problem, we present in this paper a new approach that supports mixed-criticality workload execution in a multicore processor-based embedded system. It allows any number of cores to run less-critical tasks concurrently with the critical core, which is running the critical task. The approach is based on the use of a dedicated Deadline Enforcement Checker (DEC) implemented in hardware, which allows the execution of any number of cor
- Publication Date: 29-Aug-2015
- DOI: 10.15224/978-1-63248-073-6-05
- Views: 0
- Downloads: 0