Loading...
  • Home
  • Search Results
245-246 of 4327 Papers

A SUB-PIPELINED IMPLEMENTATION OF AES FOR ALL KEY SIZES

Published In: 1ST INTERNATIONAL CONFERENCE ON ADVANCES IN COMPUTER, ELECTRONICS AND ELECTRICAL ENGINEERING
Author(s): M.S. SUTAONE , P.V.SRINIWAS SHASTRY

Abstract: In this paper we have proposed three sub-pipelined architectures for Encryption, Decryption and Joint Encryption and Decryption (E/D). These architectures were implemented on Vertex-4 device. The use of Block RAM available in the device for key expansion as well as for the S-Boxes resulted in utilizing less slices and getting higher throughput in all three cases compared to the literature available till date. The encryption architecture clocked a throughput of 35.65Gbps using only 4823 slices while the decryption architecture achieved 33.73Gbps using 6847 slices only. The device used is XC4VLX60. The joint E/D architecture achieved a throughput of 31.62Gbps. Retiming techniques used to balance the computational path delays of encryption and decryption data paths.

  • Publication Date: 12-Mar-2012
  • DOI: 10.15224/978-981-07-1847-3-810
  • Views: 0
  • Downloads: 0

A SUB-PIPELINED IMPLEMENTATION OF AES FOR ALL KEY SIZES

Published In: 1ST INTERNATIONAL CONFERENCE ON ADVANCES IN COMPUTER, ELECTRONICS AND ELECTRICAL ENGINEERING
Author(s): M.S. SUTAONE , P.V.SRINIWAS SHASTRY

Abstract: In this paper we have proposed three sub-pipelined architectures for Encryption, Decryption and Joint Encryption and Decryption (E/D). These architectures were implemented on Vertex-4 device. The use of Block RAM available in the device for key expansion as well as for the S-Boxes resulted in utilizing less slices and getting higher throughput in all three cases compared to the literature available till date. The encryption architecture clocked a throughput of 35.65Gbps using only 4823 slices while the decryption architecture achieved 33.73Gbps using 6847 slices only. The device used is XC4VLX60. The joint E/D architecture achieved a throughput of 31.62Gbps. Retiming techniques used to balance the computational path delays of encryption and decryption data paths.

  • Publication Date: 12-Mar-2012
  • DOI: 10.15224/978-981-07-1847-3-810
  • Views: 0
  • Downloads: 0