THE IMPORTANCE OF INFORMATION SHARING AUTOMATION FOR UNIVERSITY TIMETABLE PLANNING
Published In: 2ND INTERNATIONAL CONFERENCE ON ADVANCES IN INFORMATION PROCESSING AND COMMUNICATION TECHNOLOGY
Author(s): ABU BAKAR MD SULTAN , NAJLAA ATEEQ MOHAMMED DRAIB
Abstract: University timetable planning is one of the major management activities for any universities in the world. The quality of the timetabling would ensure the smooth registration process by students and avoided unnecessary adjustment. The quality of university timetable is determined by the degree of soft constraint satisfied while hard constraints cannot be compromised. Timetabling problem is the classic problem for computer science domain. Over the past three decades many research has been carried but mostly focusing on the methods or techniques rather than information sharing. Heuristics approaches such as evolutionary computing was the most appeared in literatures. The complexities and size of the problem depends on many factors such as total number of courses from different departments, and resources such as lectures, rooms and timeslots. The cross departmental academic courses registration increases the complexity that requires good communication to avoid missing courses that suppose
- Publication Date: 19-Apr-2015
- DOI: 10.15224/978-1-63248-044-6-15
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DESIGN AND ANALYSIS OF A CFCFC OTA BASED ON THE BEHAVIORAL MODELING OF A 4TH ORDER LOW-PASS HYBRID ΣΔ MODULATOR
Published In: 2ND INTERNATIONAL CONFERENCE ON ADVANCES IN INFORMATION PROCESSING AND COMMUNICATION TECHNOLOGY
Author(s): D. CALDERON-PRECIADO , E. CH. BECERRA-ALVAREZ , F. SANDOVAL-IBARRA , J. G. GARCIA-SANCHEZ
Abstract: In this paper SIMSIDES-based behavioral simulation of a 4th order Hybrid ΣΔ (HΣΔ) modulator was carried out to define electrical characteristics of an Analog Building Block (ABB), specifically a fully differential OTA. A set of experiments based on analytical models was defined to analyze the overall performance of the Switched Capacitor (SC) ΣΔ modulator in order to translate the design considerations into a set of values that the design at transistor level can be established by the desired performance of the chosen architecture. In accordance with this design strategy, a fully differential CFCFC OTA was designed according to design rules of a 130nm CMOS process. Simulation results show that an open-loop gain A0 = 60dB, and unity-gain bandwidth f0dB = 1.0GHz are enough to obtain a Signal-to-Noise Ratio (SNR) of 68dB (±1dB) when this OTA is added to the DT ΣΔ modulator. Furthermore the hand-made small-signal analysis of the chosen OTA topology allow us to obtain an analytic design mode
- Publication Date: 19-Apr-2015
- DOI: 10.15224/978-1-63248-044-6-14
- Views: 0
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