ANALYSIS OF LEVEL SHIFTED MODULATION STRATEGIES APPLIED TO CASCADED H-BRIDGE MULTI-LEVEL INVERTER FED INDUCTION MOTOR DRIVE
Published In: 6TH INTERNATIONAL CONFERENCE ON ADVANCES IN COMPUTING, CONTROL AND NETWORKING
Author(s): E. SREENU , P. SATISH KUMAR , RAVI KUMAR BHUKYA
Abstract: This paper presents various level shifted multi carrier PWM techniques such as PD,POD and APOD for a cascaded H-Bridge multi level inverter fed induction motor drives. The performance analysis of these modulation strategies are analyzed by apply for five level, seven level, nine level and eleven level inverter. The performance analysis of cascaded H-Bridge interms of line voltage, stator current, speed, torque and total harmonic distortion. The results are depicting that PD-PWM is more effective among the three proposed PWM techniques. The proposed technique has been simulated using MATLAB/SIMULINK software. These Level shifted PWM techniques can be applied to N-level cascaded Inverter also.
- Publication Date: 26-Feb-2017
- DOI: 10.15224/978-1-63248-117-7-18
- Views: 0
- Downloads: 0
A NEW GENERALIZED ASYMMETRICAL CASCADE MULTILEVEL INVERTER TOPOLOGY WITH REDUCED POWER ELECTRONIC SWITCHES AND DC SOURCES
Published In: 6TH INTERNATIONAL CONFERENCE ON ADVANCES IN COMPUTING, CONTROL AND NETWORKING
Author(s): P. SATISH KUMAR , G. SRIDHAR , M. SUSHAMA
Abstract: In the past few years the demand for the achievements in development of multilevel inverter topologies has been increasing a lot. Recently presented topologies accomplish higher number output voltage levels with few number of switches, DC voltage sources, and reduced voltage stress across switches, with fewer losses as compared with conventional topologies. Minimization of switches and dc voltage sources reduces complexity, cost size and improves the overall performance. These benefits are proposed in this paper with a new topology of asymmetrical cascaded multilevel inverter. This developed structure provides reduced number of controlled switches, DC sources, as compared with conventional and presented topologies in the literature so far. The proposed asymmetrical topology generates seven voltage levels with eight switches only. Furthermore reduction in voltage stress across the switches can be attained. Phase Opposition Disposition (POD) is adopted for generating switching pulses. Th
- Publication Date: 26-Feb-2017
- DOI: 10.15224/978-1-63248-117-7-19
- Views: 0
- Downloads: 0