GENERATING MULTI SERVER ENVIRONMENT FOR IMPLEMENTATION OF IDEAL PASSWORD AUTHENTICATION SCHEME
Published In: INTERNATIONAL CONFERENCE ON ADVANCES IN ELECTRONICS, ELECTRICAL AND COMPUTER SCIENCE ENGINEERING
Author(s): G.GEETHA , KULJEET KAUR
Abstract: Ideal Password Authentication Scheme comprises of two identity authentication parameters Fingerprint and Password. When two identity authentication parameters are used then for fortification of transport layer, mutual authentication is done in the Multi Server Environment of an organization. Paper elucidates the process for generating Multi Server Environment in an Organization. Complete implementation of ideal password authentication scheme in the multi server environment of an organization is revealed in the paper. Proof is derived in the paper that mutual authentication if done in the multi server environment of an organization then Phishing, IP Spoofing and Server spoofing would almost diminish. Overall paper concludes that intruders or hackers would be unable to spoof or hack at any level at the transport layer in multi server environment and fortification of transport layer security protocol is proved.
- Publication Date: 09-Jul-2012
- DOI: 10.15224/978-981-07-2950-9-9376
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A SOC BASED LOW POWER 8-BIT FLASH ADC IN 45 NM CMOS TECHNOLOGY
Published In: INTERNATIONAL CONFERENCE ON ADVANCES IN ELECTRONICS, ELECTRICAL AND COMPUTER SCIENCE ENGINEERING
Author(s): P. SHARMA , R. DUTTA
Abstract: In modern VLSI design the transistor sizing and scaling has an considerable impact. There are very essential two constrains, which needs serious attention to the VLSI chip designer are high speed and low power consumption. Therefore in this paper an 8-bit 3 Gs/sec flash analog-to-digital converter (ADC) in 45nm CMOS technology is presented for low power and high speed system-on-chip (SoC) applications. This low power 8-bit flash Analog to Digital converter comprises 255 comparators and one thermometer to binary encoder. This flash ADC design is an extended research work of the earlier work related to ADC design using CMOS process technology. The schematic simulation of ADC is done in Tanner-Spice Pro (SEdit) and layout simulation is done in Tanner-Spice Pro (L-Edit) V.15.14. The Simulated result shows the power consumption in Flash ADC is 41.78μw. The Threshold Inverter Quantization (TIQ) technique is proposed to get WPMOS/WNMOS < 1 for transistors to keep the power consumption as low
- Publication Date: 09-Jul-2012
- DOI: 10.15224/978-981-07-2950-9-9391
- Views: 0
- Downloads: 0