Abstract: A new Cache memory cell has been proposed using the DCI logic gate. The principle and operation of the cell has been given. The current equation at each stage of the memory cell has been deduced. The dynamic response of the cell has been obtained by computer-simulation. The performance of our Cache memory cell has been compared with that of the IBM Cache memory cell. The cycle and access time of the proposed cell are 250ps and 210ps respectively, compared to earlier Cache memory cycle and access times, 1000ps and 650ps, respectively. Our Cache memory cycle time and access time can be further reduced since it is based on the DCI logic, which does not have much restriction on its size.

• Publication Date: 09-Jul-2012
• DOI: 10.15224/978-981-07-2950-9-9426
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Abstract: The accuracy and effectiveness of a Wireless Sensor Network depends on how efficiently the nodes can be localized and thus the cognizant of their position is of utmost importance. The presence of Non Line of Sight (NLOS) channel condition between the sensor nodes is one of the major hindrances for accurate ranging and localization in WSN. As a result there is a need for low complexity and robust algorithm which can effectively identify the channel condition and help in further mitigation of NLOS rangingerrors byusing an appropriate method. In this paper, we have proposed a very low complexity algorithm that only requires the RSSI (requiring no complex external hardware) for estimating the channel condition which can either be LOS or NLOS.This gives us an advantage and freedom of tackling the NLOS ranging using any amongst various suitable methods developed so far with no extra cost to bear.

• Publication Date: 09-Jul-2012
• DOI: 10.15224/978-981-07-2950-9-9428
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