AN IMPROVED SPEAKER RECOGNITION BY HMM
Published In: INTERNATIONAL CONFERENCE ON ADVANCES IN ELECTRONICS, ELECTRICAL AND COMPUTER SCIENCE ENGINEERING
Author(s): AMRUTA ANANTRAO MALODE , SHASHIKANT L. SAHARE
Abstract: The domain area of this topic is Bio-metric. Speaker Recognition is biometric system. This paper deals with speaker recognition by HMM (Hidden Markov Model) method. The recorded speech signal contains background noise. This noise badly affects the accuracy of speaker recognition. Discrete Wavelet Transforms (DWT) greatly reduces the noise present in input speech signal. DWT often outperforms as compared to Fourier Transform, due to its capability to represent the signal precisely, in both frequency & time domain. Wavelet thresholding is applied to separate the speech and noise, enhancing the speech consequently. The system is able to recognize the speaker by translating the speech waveform into a set of feature vectors using Mel Frequency Cepstral Coefficients (MFCC) technique. Hidden Markov Model (HMM) provides a highly reliable way for recognizing a speaker. Hidden Markov Models have been widely used, which are usually considered as a set of states with Markovian properties and obser
- Publication Date: 09-Jul-2012
- DOI: 10.15224/978-981-07-2950-9-9771
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A DA SERIAL MULTIPLIER TECHNIQUE BASED ON 32-TAP FIR FILTER FOR AUDIO APPLICATION
Published In: INTERNATIONAL CONFERENCE ON ADVANCES IN ELECTRONICS, ELECTRICAL AND COMPUTER SCIENCE ENGINEERING
Author(s): ASHISH RAMAN , DINESH CHAND GUPTA , K BALRAJ
Abstract: This paper presents the design and implementation of a high speed 32-tap finite impulse response (FIR) filter that employs the Distributive Arithmetic (DA) technique for the complex computation of Audio Coefficients and Multipliers. Distributive Arithmetic (DA) has been used to implement a bit-serial scheme of a general symmetric version of FIR filter due to its high stability and linearity by taking optimal advantage of the look-up table (LUT), base structure of Field Programmable Gate Array (FPGA). Distributive Arithmetic algorithm (DA-FIR) technique is employed for reducing the complex computations, thereby increasing the speed and it also reduces the area and power consumption. The design is modeled using Verilog HDL and implemented on Virtex II Pro FPGA that consumes 39% resources of FPGA and shows the clock latency of 34 cycles at 192.45 MHz clock frequency.
- Publication Date: 09-Jul-2012
- DOI: 10.15224/978-981-07-2950-9-9778
- Views: 0
- Downloads: 0