COLOR BLIND IMAGE CORRECTION
Published In: INTERNATIONAL CONFERENCE ON ADVANCES IN ELECTRONIC DEVICES AND CIRCUITS
Author(s): A. A. M. A. SHAFIEE , M. S. MUHAMMAD , S. M. W. MASRA
Abstract: Color blindness or color vision deficiency (CVD) refers to the inability to perceive or distinguish certain colors or shades of colors to some degree. This paper presents different methods of correcting images especially for people suffering from dichromacy: protanopia, deuteranopia and tritanopia. Color transformation, color simulation and colormap approximation are the methods that have been applied in this project for helping color blind people to improve color perception when they see things in this world. Experimental results demonstrate the effectiveness of the proposed methodology. A survey has been conducted to colorblind people to test the proposed methodology.The output of the survey shows very promising results, indicating that the proposed method of image correction using colormap approximation method is capable of relaying information in the picture or image tothe color blind people.
- Publication Date: 05-May-2013
- DOI: 10.15224/978-981-07-6261-2-48
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AN FPGA EMBEDDED ACCA ARCHITECTURE FOR HIGH RESOLUTION TARGET DETECTION
Published In: INTERNATIONAL CONFERENCE ON ADVANCES IN ELECTRONIC DEVICES AND CIRCUITS
Author(s): RIDHA DJEMAL
Abstract: This paper presents an efficient FPGA-based architecture of CFAR target detector for radar system based on the automatic censored cell averaging (ACCA) detector based on ordered data variability (ODV). The ACCA–ODV detector estimates the unknown background level by dynamically selecting a suitable set of ranked cells and applying successive hypothesis tests. The proposed detector does not require any prior information about the non homogenous background environment. It uses the variability index statistic as a shape parameter to accept or reject the ordered cells under investigation. The detection process is achieved on the fly in real-time where the processing time must be lower than 0.5 µs for high resolution detection. The proposed architecture is based on the embedded software solution which consists on execution an the ANSI-C code of the detector over the Nios-II soft-core processor downloaded in the FPGA with the requires hardware components, such as on-chip memories, UART and JT
- Publication Date: 05-May-2013
- DOI: 10.15224/978-981-07-6261-2-47
- Views: 0
- Downloads: 0