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VHDL IMPLEMENTATION OF AES-128

Published In: INTERNATIONAL CONFERENCE ON RECENT TRENDS IN COMPUTING AND COMMUNICATION ENGINEERING
Author(s): PURNIMA GEHLOT , RICHA SHARMA , S.R BIRADAR

Abstract: Security has become an increasingly important feature with the growth of electronic communication. The Symmetric in which the same key value is used in both the encryption and decryption calculations are becoming more popular. The AES algorithm is capable of using cryptographic keys of 128, 192, and 256 bits to encrypt and decrypt data in blocks of 128 bits. This standard is based on the Rijndael algorithm. In this project our main concern is to implement all modules of this algorithm on hardware.This methodology uses VHDL implementation of all the modules in terms of Delay and Frequency.

  • Publication Date: 21-Apr-2013
  • DOI: 10.15224/978-981-07-6184-4-37
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TWOFISH ALGORITHM AND ITS IMPLEMENTATION ON FPGA

Published In: INTERNATIONAL CONFERENCE ON RECENT TRENDS IN COMPUTING AND COMMUNICATION ENGINEERING
Author(s): PURNIMA GEHLOT , RICHA SHARMA , S.R BIRADAR

Abstract: Now-a-days internet is one of the most important source of communication and thousands of people interact electronically. For sending sensitive messages over the internet, we need security. In this paper a security algorithm, Twofish has been explained with all of its modules with both 128 and 192-bit key size. Implementation on Xilinx – 6.1 xst software has been done taking delay as main constraint.

  • Publication Date: 21-Apr-2013
  • DOI: 10.15224/978-981-07-6184-4-38
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