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ANALYSIS OF TWO & THREE LEVEL DIODE CLAMPED MULTILEVEL INVERTER FED PMSM DRIVE USING SPACE VECTOR PULSE WIDTH MODULATION (SVPWM)

Published In: INTERNATIONAL CONFERENCE ON ADVANCES IN COMPUTER, ELECTRONICS AND ELECTRICAL ENGINEERING
Author(s): G. SREE LAKSHMI , S. KAMAKSHAIAH , TULASI RAM DAS

Abstract: This paper proposes implementation of Two and Three Level Diode-Clamped Multilevel inverter using IGBT’s fed to both built -in and mathematical model of PMSM drive. The pulses for the inverters have been developed by using Space Vector Pulse Width Modulation Technique (SVPWM). Space Vector Pulse Width Modulation Technique is most prominent PWM technique for three phase voltage source inverters for the control of AC Induction Motors, Brushless DC Motors, Switched Reluctance and Permanent Magnet Synchronous Motors. The output voltages, currents, torque and speed characteristics have studied for two and three-level inverters fed to both mathematical model and built -in model. It has observed that both have same results. Three -level inverter can use more DC link voltage than two- level inverter and also SVPWM Technique utilizes DC bus voltagemore efficiently and generates less harmonics.

  • Publication Date: 28-Apr-2013
  • DOI: 10.15224/978-981-07-6260-5-20
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A NOVEL APPROACH TO CONSTRUCT ONLINE TESTABLE REVERSIBLE LOGIC

Published In: INTERNATIONAL CONFERENCE ON ADVANCES IN COMPUTER, ELECTRONICS AND ELECTRICAL ENGINEERING
Author(s): DEBAJYOTY BANIK

Abstract: Reversible logic is emerging as an important research area having its application in diverse fields. Reversible circuits can be used in the fields of low-power computation, cryptography, digital signal processing, communications and the emerging field of quantum computation. Regardless of the eventual technology adopted, testing is sure to be an important component in any robust implementation. A new approach for automatic conversion of any given reversible circuit into an online testable circuit that can detect online any single-bit errors, including soft error in logic block is described in this paper.

  • Publication Date: 28-Apr-2013
  • DOI: 10.15224/978-981-07-6260-5-21
  • Views: 0
  • Downloads: 0