Abstract: Switch-capacitor (SC) circuits are one of the most popular methods for implementing signal processing blocks such as Integrator, Filters, ADC in CMOS technology. This is primarily due to accurate time constant realization over a wide temperature and process corners. Beside good voltage linearity SC circuits occupies less area than continuous time circuits. Non-overlapping clock (NOC) generator is one of the important blocks of any SC circuit. In standard NOC design, simple CMOS inverters are connected in cascade to implement delay blocks. As technology scales, number of inverter increases affecting the area and power budget of the design. In this work, it is proposed to use two numbers of inverted CMOS inverters and one current starved inverter in cascade as a delay block, to achieve a larger delay for a given area. The proposed delay block is used to realize a ring oscillator and a voltage controlled NOC generator. Simulation result shows that proposed delay block exhibits a larger de

• Publication Date: 28-Apr-2013
• DOI: 10.15224/978-981-07-6260-5-42
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Abstract: The power system studies are required to evaluate the performance of the system at planning stage as well as running conditions. This paper presents short circuit analysis of an industrial electrical power distribution system in compliance to IEC 60909. Short-circuit studies can be performed at the planning and design stage in order to help finalize the system layout, determine voltage levels, protection equipments, switchgears, and cables size, transformers, grounding and earthing. The industrial distribution system is simulated on ETAP software and different fault study is performed.

• Publication Date: 28-Apr-2013
• DOI: 10.15224/978-981-07-6260-5-41
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• Downloads: 0