Abstract: The main objective of this paper is to describe an efficient hardware-based concept of a digital video WM system which features low power consumption, efficient and low cost implementation, high processing speed, reliability and invisible, semi-fragile watermarking in compressed video streams. The presented WM system can be integrated with video compressor unit and it achieves performance that matches complex software algorithms within a simple efficient hardware implementation. The system also features minimum video quality degradation and can withstand certain potential attacks i.e. cover-up attack, cropping, segment removal on video sequences. The proposed WM system is implemented using Verilog hardware description language (HDL) synthesized into a field programming gate array (FPGA) and then experimented using a custom versatile breadboard for performance evaluation is describe through various research papers which give a vital review related to digital video watermarking system fo

• Publication Date: 28-Apr-2013
• DOI: 10.15224/978-981-07-6260-5-34
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Abstract: Continuously scaling down devices is the main goal in deep sub-micron (DSM) technology. Though using DSM technology we are achieving many advantages. But circuit performances are badly affected because of secondary effects like crosstalk noise. According to International Technical Roadmap for Semiconductors(ITRS) 2011 report today’s DSM technology outsmarted Moore’s law to work in a new industrial trend called “More than Moore” (MtM). To accomplish this, it is necessary to analyze the timing behavior of the interconnect. Decoupling capacitor can have significant effect on principal characteristics of an integrated circuit (IC) i.e. speed, cost and power. So by including a decoupling capacitor intentionally can control secondary effects in very deep sub-micron (VDSM) technology. But inserting a decoupling capacitor affects delay and bandwidth of the interconnect. So while inserting decoupling capacitor we have to check for the disturbances in delay and bandwidth. Here in this paper two

• Publication Date: 28-Apr-2013
• DOI: 10.15224/978-981-07-6260-5-38
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