Abstract: The Logical Effort model is mainly to reduce delay in a circuit, but does not show how to minimize power and area. This paper deals with an empirical modeling and design of logical effort for estimating power in CMOS logic gates. The power is estimated in a circuit using the power of standard inverter and the relationship established between Power (P) and Logical Effort (g), Electrical Effort (h) and Parasitic (p) have been proposed in this paper. To verify the above model a full adder circuitry producing just the carry-out in UMC 90nm CMOS technology having supply voltage of 1V is selected. The results obtained from the model are accurate to 85.5% of the values obtained. The tool used is cadence and the simulation is performed using spectrum".

• Publication Date: 12-Mar-2012
• DOI: 10.15224/978-981-07-1847-3-511
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Abstract: Water pollution is one of the key threats for the green globalization. To prevent the water pollution, first we have to detect the pollutant. In earlier days, the water pollution was detected by chemical test or laboratory test by using this system the testing equipment will be in stationary and samples will be given to testing equipment. In order to increase the pervasiveness, testing equipment can be placed in the river water and detection of pollution can be made remotely. This paper proposes a Sensor-Based Water Pollution Detection, which will detect the pollutant present in the water and give an alert massage to the agent. The sensor pH, turbidity and DO will be kept in the river water surface and the data captured by the sensor will be given to PIC Micro controller, and then the data are transmitted wirelessly using Zigbee module. After calculating the inference from the sensed data, In case of inference value above the threshold value automated warning SMS alert will be sent to

• Publication Date: 12-Mar-2012
• DOI: 10.15224/978-981-07-1847-3-517
• Views: 0
• Downloads: 0