1. ANALYSIS OF PSEUDO-NMOS LOGIC WITH REDUCED STATIC POWER IN DEEP SUB-MICRON REGIME

Authors: M. JANAKI RANI , S. MALARKKAN

Abstract: The growing demand for high density VLSI circuits result in scaling of supply voltage and an exponential increase of leakage or static power in deep sub-micron technology. Therefore reducing static power consumption of portable devices such as cell phones and laptop computers is highly desirable for a longer battery life. In this paper we propose two power reduction techniques such as reverse body bias and transistor stacking for reducing the static power of Pseudo NMOS logic circuits that have very high static power consumption. The simulation results show that the static power decreases with both the methods and the combined effect of reverse body bias and stack method gives the least static current. The simulations are done at 65nm and 45nm process technologies using HSPICE at a temperature of 27C with two different supply voltages of 1v and 0.3v.

Keywords: Pseudo-NMOS logic, process technology, reverse body bias, transistor stack, static power.