TECHNIQUES TO DISCOVER BLACK HOLE NODES IN MOBILE AD HOC NETWORKS USING AODV PROTOCOL
Published In: INTERNATIONAL CONFERENCE ON ADVANCES IN ELECTRONICS, ELECTRICAL AND COMPUTER SCIENCE ENGINEERING
Author(s): PUJA , R.K.SINGH , TANU PREET SINGH , V.K BANGA
Abstract: A wireless Adhoc network is a collection of mobile nodes with no pre-established infrastructure, forming a temporary network. In the absence of a fixed infrastructure, nodes have to cooperate in order to provide the necessary network functionality. One of the principal routing protocols used in Ad hoc networks is AODV (Ad hoc On-Demand Distance Vector) protocol. The security of the AODV protocol is compromised by a particular type of attack called ‘Black Hole’ attack [1]. In this attack a malicious node advertises itself as having the shortest path to the node whose packets it wants to intercept. It is proposed to wait and check the replies from all the neighboring nodes to find the Black hole nodes. In this paper, we detect the Black hole nodes or malicious nodes and after detecting it we will remove those nodes and also find the shortest path from source to destination by using GLOMOSIM. We propose that our protocol is increase the throughput, security and life time of the network by
- Publication Date: 09-Jul-2012
- DOI: 10.15224/978-981-07-2950-9-9400
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ANALYSIS AND SIMULATION OF A LOW-LEAKAGE 10T SRAM BIT-CELL USING DUAL-V TH SCHEME AT DEEP SUB MICRON CMOS TECHNOLOGY
Published In: INTERNATIONAL CONFERENCE ON ADVANCES IN ELECTRONICS, ELECTRICAL AND COMPUTER SCIENCE ENGINEERING
Author(s): MANISHA PATTANAIK , R.K.SINGH , S.BIRLA , SVEEN NAGPAL , NEERAJ KR. SHUKLA
Abstract: Exponential growth of battery powered portable applications demanding new SRAM cell topologies with low-leakage. In this work, an analysis and simulation on P-P-N based 10T SRAM cell using dual-Vth scheme (at deep sub-micron technology) is presented. This work achieved stand-by leakage reduced by 74% and 77% at VDD=0.8V and VDD=0.7V respectively without losing cells performance at an area power trade-off. The simulation is being performed at 45nm CMOS technology, Vthn = 0.22V, Vthp = 0.224V, VDD = 0.7 and 0.8V, and at T=27°C.
- Publication Date: 09-Jul-2012
- DOI: 10.15224/978-981-07-2950-9-9403
- Views: 0
- Downloads: 0