A ROBUST APPROACH FOR CONSTRUCTION OF IRREGULAR LDPC CODES
Published In: INTERNATIONAL CONFERENCE ON FUTURE TRENDS IN ELECTRONICS AND ELECTRICAL ENGINEERING
Author(s): ASHISH GOSWAMI , RAKESH SHARMA
Abstract: The future communication systems aim at effective error control coding methods with effective error performance and considerable code rates. LDPC codes are again gaining popularity in future communication systems due to ease in encoding design, effective BER and accept-able code rate. This paper presents a new method for constructing an irregular LDPC codes from low column weight LDPC codes. It is discussed that theproposed method has simple encoding process and less memory requirements. It has been shown that proposed method improves BER performance on AWGN channel by approx. 1 dB per extension level with only slight reduction in code rate.
- Publication Date: 14-Jul-2013
- DOI: 10.15224/978-981-07-7021-1-69
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A LOW-POWER SAMPLE-AND-HOLD AMPLIFIER USING 0.05-ΜM CMOS TECHNOLOGY
Published In: INTERNATIONAL CONFERENCE ON FUTURE TRENDS IN ELECTRONICS AND ELECTRICAL ENGINEERING
Author(s): HIMANSHU PUNDIR , RITURAJ SINGH RATHORE , VINOD KUMAR
Abstract: This paper presents a sample-and-hold circuit based on a cascode-miller compensation technique, utilizing a class-AB operational amplifier as an output stage. Also using the techniques of pre-charging and output capacitor coupling can mitigate the requirements for the op-amp, resulting in low power dissipation. Power consumption is about 300µW from a single 1-V power supply. The performance of this SHA is not degraded even if input frequency approaching up to Nyquist frequency.
- Publication Date: 14-Jul-2013
- DOI: 10.15224/978-981-07-7021-1-40
- Views: 0
- Downloads: 0