Abstract: This paper presents a design of a 8 transistor one-bit full adder cell with Double Gate MOSFET. This design has been compared with existing 8 transistor one-bit full adder cell using Single Gate MOSFET at 45nm technology in sub threshold region. In this paper, the designed circuits are observed keeping the power consumption and Power Delay Product as parameters. Simulations are performed on SPICE tool and they have verified the correct operation of the full adder cell using Double Gate MOSFET for a variety of inputs at different supply voltages, temperatures and frequencies. Results indicated that the full adder with Double Gate MOSFET is capable of significant improvement in power consumption and Power Delay Product.

• Publication Date: 25-May-2014
• DOI: 10.15224/978-1-63248-028-6-02-25
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Abstract: In this paper a new logic technique and hence circuit design has been proposed for the implementation of magnitude comparator. This proposed 2-Bit magnitude comparator is design to improve power consumption as well as on-chip area than its peer design. The proposed 2-Bit magnitude comparator has threshold loss of 13%-20%. This threshold loss is due to PTL (Pass Transistor Logic) logic applied at the input end and at the output end TG (Transmission Gate) logic is used, this is done to reduce the number of transistor. The schematic of 2-Bit magnitude comparator is designed using Tanner EDA Tool version 12.6 at 45nm technology.

• Publication Date: 25-May-2014
• DOI: 10.15224/978-1-63248-028-6-02-26
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